library verilog;
use verilog.vl_types.all;
entity led is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        load            : in     vl_logic;
        in_data         : in     vl_logic_vector(15 downto 0);
        seg             : out    vl_logic_vector(7 downto 0);
        sel             : out    vl_logic_vector(2 downto 0)
    );
end led;
